Power conversion devices, such as DC/AC or AC/AC inverters, typically contain switching elements which are implemented as gate turn-off devices such as transistors. Despite the clear advantages of using these self-commutating switching devices over, for example, thyrister switches, the inherent characteristics of available transistor switches impose several performance limitations on inverters employing them. Many of these limitations stem from the turn-on and turn-off losses associated with the switching devices. Switching losses limit the attainable switching frequency. Relatively low switching frequencies can cause acoustic noise problems. Low switching frequencies also result in low amplifier bandwidth and poor load current waveform fidelity (unwanted harmonics). Moreover, the reverse recovery and snubber interactions between the switching device and its associated anti-parallel diode cause high device stresses under regeneration conditions. In turn, the need to withstand the high device stresses reduces reliability and requires that the devices by overspecified. These limitations are characteristic of "hard-switching" inverters wherein the inverter switching elements are switched between the conducting and non-conducting states in the presence of relatively high DC voltages.
Ideally, a power converter should have essentially zero switching losses, a high switching frequency, small reactive components and the ability to transfer power bi-directionally. The system should also be insensitive to second order parameters such as diode recovery times, device turn-off characteristics and parasitic reactive elements.
So-called "soft-switching" inverters offer several of these advantages over standard inverter designs, including virtually zero switching losses, and the associated advantages of high switching speed and moderate dv/dt stresses. In soft-switching power converters, the inverter switching devices are only switched at points in time where there is either no voltage across or no current through the switching device. One such soft-switching topology is the resonant DC link inverter, a circuit which has been shown to be viable in both its voltage source and current source versions. FIG. 1 is a circuit diagram of a conventional, three-phase, resonant DC link inverter. The two main components of the DC resonant link inverter are the DC resonant link 10 and the inverter circuit 17 which are connected at the DC bus terminals 15 and 16. The DC resonant link 10 includes a DC voltage power supply 11, a series DC resonant link inductor 12 (of inductance L), a capacitor 13 (of capacitance C), and a gaited switching device 14 connected across the DC bus terminals 15 and 16 of the resonant link. The inductor 12 and capacitor 13 are connected to form a resonant tank circuit.
To illustrate the operation of the resonant circuit 10, assume that the power supply 11 is initially disconnected from the circuit. If the voltage V.sub.s from the power supply 11 is now applied to the system with the switch 14 off (open circuited), for a loss-less inductor 12 and capacitor 13, the output voltage V.sub.o (with the terminals 15 and 16 disconnected from the inverter circuit 17) will vary between V.sub.s and zero and have an average value of one-half V.sub.s, with the output voltage varying at the resonant frequency of the LC resonant circuit composed of the inductor 12 and capacitor 13. Every cycle, the output voltage V.sub.o will return to zero volts, thus setting up the desired condition where loss-less switching may take place. For practical LC circuits having finite Q factors, the output voltage V.sub.o will never return to zero and will finally stabilize at V.sub.s. However, if the switch 14 is maintained on and conducting while applying the voltage V.sub.s from the power supply 11, the current in the inductor 12 increases linearly. The switch 14 may then be turned off when sufficient energy is stored in the inductor to ensure that the output voltage V.sub.o will return to zero. At that point, the switch 14 may be turned on once again to repeat the process and establish a stable oscillation of the resonant circuit 10, thereby forming a stable DC resonant link voltage at the DC bus terminals 15 and 16.
The inverter circuit 17 is of standard design, composed of pairs of gate turn-off switching devices (e.g., bi-polar transistors) 20 and 21, 22 and 23, and 24 and 25, having output lines 27, 28 and 29 on which voltages V.sub.A, V.sub.B and V.sub.C are provided. Each of the switching devices 20-25 is synchronized to switch at the points in time at which the voltage across the DC bus terminals 15 and 16 goes to zero.
Many other designs for resonant and quasi-resonant power conversion circuits are possible. Other circuit designs may be found in U.S. Pat. Nos. 4,730,242, 4,833,584, and 4,864,483, to Divan, and U.S. Pat. No. 4,942,511 to Lipo, et al., the disclosures of which are incorporated herein by reference.
An inverter modulator is a device which generates control signals for switching the switching devices of an inverter 20-25 in a proper sequence to synthesize an AC waveform on the output lines 27-29 from the DC voltage at the DC bus terminals 15-16. This is accomplished through modulation and switching at a frequency much higher than the frequency of the AC output waveform. The high frequency components of the output waveforms which result from the modulation and switching may be filtered by the loads to which the output lines 27-29 are attached. For example, where the load is an uninterruptible power supply (UPS) the high frequency components of the output may be filtered by transformers or a low pass filter. Where the load is a machine, filtering may be provided by the machine's leakage inductance. In this way, an output signal approximating a sine wave may be achieved. However, any modulation scheme will not produce a perfect sine wave output signal. Some modulation noise may be present on the output voltage signal. The quality of the output voltage signal is determined by the signal-to-noise ratio (SNR) of the output signal.
In the soft-switching resonant DC link inverter, low switching losses are realized by turning the switching devices 20-26 on and off when the bus voltage is zero, an event that occurs almost periodically at a rate given by the bus oscillation frequency. The constraint of switching only at times of zero bus voltage requires a discrete pulse modulation (DPM) scheme for inverter switching control, rather than a more conventional pulse width modulation (PWM) switching scheme employed with hard-switched inverters.
Under PWM, the turn-on and turn-off times of the inverter switching devices 20-25 are varied, thereby varying the duration of the DC pulses which appear on the output lines 27-29, to synthesize an AC output waveform. However, for the resonant DC link inverter, the switch-on and switch-off times are constrained by both the waveform to be synthesized and by the frequency of the resonant link. Since the switching of the switching devices 20-25 is limited to those points in time when the bus voltage is zero, a form of discrete pulse modulation (DPM) must be used.
A modulator implementation that has been used previously to provide discrete pulse modulation of a resonant DC link inverter is the simple interpolative sigma-delta modulator shown in its simplest form in FIG. 2. In this figure, x(t) is the input or reference signal, u(t) is a signal representing the state of the integrator 34, and y(t) is the output of the latch 31. The integrator state signal u(t) is derived from the difference between the reference signal x(t) and the modulator output y(t). The comparator 35 may be thought of as a simple quantizer whose output q(u) is +b or -b according to the sign of the integrator state signal u(t). The latch 31 samples the comparator or quantizer output q(u) at a sampling rate f, and holds that signal until the next sampling instant.
The sigma delta modulator 30 uses feedback to lock onto the scalar band-limited input signal x(t). Unless the reference signal x(t) exactly equals one of the discrete quantizer output levels +b or -b a tracking error results. The integrator 34 accumulates the tracking error over time, and the quantizer and latch feed back a value y(t) that will minimize the accumulated tracking error. Thus, the quantizer output y(t) toggles about the input signal x(t) so that the average quantizer output is approximately equal to the average of the input.
An equivalent discrete time model of a scalar sigma-delta modulator can be given by the following nonlinear difference equation: EQU u.sub.n+1 =x.sub.n -q(u.sub.n)+u.sub.n ( 1)
where:
x is the input signal; PA0 u is the integrator state; and PA0 q is the output of the quantizer, where: ##EQU1##
The quantizer 35 can be understood as mapping its input u to +b or -b depending on which is nearest to the input. Thus, the quantizer 35 may be referred to as a nearest neighbor quantizer.
For some design purposes, the operation of the sigma-delta modulator 30 can be analyzed by modeling the integrator 34 with its discrete time equivalent 36 and the quantization process by an additive noise source e(z) as illustrated in FIG. 3. The noise source e(z) may be assumed to be white and statistically uncorrelated. The noise source e(z) represents the introduction of an error into the linear system which is caused by the quantization. The noise source e(z) thus represents the difference between the most desired output of the modulator which would drive the average output waveform to equal the reference waveform x(z), and the actual control signal output of the modulator y(z) which can be obtained given that only two output levels are possible and that these levels can only change at times dictated by the switching frequency f.sub.s. Thus, the quantization noise e(z) is the z transform of the quantization error sequence e.sub.n defined by: EQU e.sub.n =q(u.sub.n)-u.sub.n. (3)
With this linearized model of the sigma-delta modulator, it can be shown that: EQU q(z)=x(z)z.sup.-1 +e(z)(1-z.sup.-1). (4)
To illustrate how power electronic circuits have been modulated using the simple sigma-delta modulator of FIG. 2, consider the modulator 30 of FIG. 2 as applied to a half bridge inverter 32 as shown in FIG. 4. In this arrangement the half-bridge includes two switching devices 37 and 38 which, it may be noted, may correspond to the switching devices for one phase of the three phase converter 17 of FIG. 1, where the voltages +b and -b impressed across the switching devices may correspond to the voltages on the DC bus terminals 15 and 16. The modulator 30 compares the reference signal x(t), representing a desired inverter output, with the inverter output signal y(t), and provides the resulting error signal to the integrator 34 and one bit comparator 35 with two discrete output levels. The latch 31 is sampled at a frequency f.sub.s which may be synchronized with the points in time at which the bus voltage across the switching devices 37 and 38 reaches zero. Thus, the modulator will be constrained to change the states of the switches 37 and 38 only at times of zero DC bus voltage. The switch state output of the latch 31 drives the switching devices 37 and 38 to impress +b or -b on the output voltage y(t). The comparator 35 and latch 31 set the switch state for each sampling period T=1/f, according to the sign of the input u at the sampling instant to cause the average of the inverter output signal y(t) to be approximately equal to the average of the reference signal input x(t) using feedback of the inverter output signal y(t) in the manner described above. For the basic sigma-delta modulator implementation shown in FIG. 4, one such controller would be required for each phase of a poly-phase inverter, with corresponding reference waveform inputs for each phase modulator.
Variations on the basic sigma-delta modulator implementation shown in FIG. 2 have been made. Other modulator topologies have also been proposed for resonant DC link converters. However, prior art modulators typically exhibit two shortcomings. First, the spectral performance, or signal-to-noise ratio of the output voltage signal, is not competitive with the industry standards for non-resonant link converters using standard PWM modulation schemes. Secondly, prior art modulators are not directly amenable to more complex power conversion circuits such as poly-phase, multi-level, and matrix converters.
In communications, interpolative sigma-delta modulators are practical for high rate analogue-to-digital conversion and data compression because of their simplicity and robustness against circuit imperfections. They operate by coarsely quantizing the input signal at a sampling rate much higher than the Nyquist rate. Using a combination of feedback and integration, the resulting modulation noise is pushed to higher frequencies, where it may be removed by filtering.
Over the past decade numerous advances in oversampled interpolative modulators of the type just described have appeared in the communications literature. The communications applications are, however, different in several respects to applications in power electronics. First, the modulators employed in communications are usually one-dimensional with a simple quantization scheme (single-bit quantizer) whereas in power electronics applications modulators are required to be multi-dimensional with a rather complex quantization scheme. To improve modulator performance in communications applications, the number of quantization levels may be increased via a multi-bit quantizer. This is not a feasible alternative in power electronics applications because the structure of the quantizer is constrained by the design of the power electronic circuit itself. A second point is that significant clock jitter (nonuniform sampling) is present in applications such as the resonant DC link which is not present in communications applications. Hence, modulators for power electronics applications must be capable of providing the required performance in the presence of clock jitter. Finally, the dynamic range in power electronics applications is a critical design constraint, whereas in communications it is not as important. This requires the use of bridging strategies wherein more complex modulators are degraded into simpler ones according to the required dynamic range.